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Holes are repelled-leaving behind a carrier depletion-region.Source & Drain are grounded and a positive voltage (vGS)is applied to the gate.An n channel is induced at the top of the substrate beneath the gate. In fact the path between Source & Drain (1012Ω) has very high resistanceįigure 4.2 The enhancement-type NMOS transistor with a positive voltage applied to the gate. No current flows even if vDSis applied.With no bias gate voltage, two back-to-back diodes exist in series between drain and source.It is a symmetrical device thus Drain & Source can be interchanged with no change in devices characteristics.Voltage applied to the Gate controls current flow between Source & Drain with direction from Drain to Source in channel region.

Thus Body will have no effect on operation of the device.

Drain will be at a positive voltage relative to the source, two junctions are at cutoff mode if substrate is connected to the source.

Substrate forms pn junctions with the source & drain region & is kept reversed biased all the time.

Current in gate terminal is small (10-15 A).

Insulted – Gate FET (IGFET) – gate is electrically insulated from the device body.

Metal oxide semiconductor - name is derived from its physical structure.

L Length of channel region W Width of the substrate tox Thickener of An oxide Layer.

Typically L = 0.1 to 3 mm, W = 0.2 to 100 mm, and the thickness of the oxide layer (tox) is in the range of 2 to 50 nm. Metal contact is made to Source & Drain and the substrate (Body)įigure 4.1 Physical structure of the enhancement-type NMOS transistor Cross-section.

Metal is deposited on top of the oxide layer to form the Gate electrode.

Thin Layer of Silicon dioxide (SiO2) is grown with thicker of tox= 2-50 nanometers An excellent electrical insulator.

n+ Drain (‘D’) n+ for heavily doped ‘n’ type silicon.

n+ Source (‘S’) n+ for lightly doped ‘n’ type silicon.

Two heavily doped n-type region are created.

Fabricated on a p-type substance that provides physical support for the device.

Types “n” channel enhancement MOSFET “p” channel enhancement MOSFET.

Implement digital & analog functions with a fewer resistors very large scale Integrated (VLSI) circuit įigure 4.1 Physical structure of the enhancement-type NMOS transistor:.NMOSFET/PMOSFET n/p-channel enhancement mode MOSFET.

1930 was Known, 1960s Commercialized 1970s Most commonly used VLSI.Uni-polar Current is conducted by only one carrier.FET Field Effect Transistor The current controlled mechanism is based on an electric field established by the voltage applied to the control terminal – GATE.MOS Metal Oxide Semiconductor Physical Structure.MOSFET ( Voltage Controlled Current Device)